1. Field of the Invention
The present invention is directed generally toward semiconductor memory cell arrays, and more particularly, toward high density storage capacitor structures in dynamic random access memory (DRAM) arrays.
2. Description of the Prior Art
Recently, a semiconductor memory device has been rapidly developed. In a random access memory (RAM), various trials have been made for achieving high integration without decreasing the storage characteristics.
FIG. 1 is a block diagram showing an example of a structure of a conventional RAM. Referring to FIG. 1, a plurality of word lines and a plurality of bit lines are arranged to intersect with each other in a memory cell array 1, a memory cell being provided at each of intersections of the word lines and the bit lines. The memory cell is selected based on an intersection of a single word line selected by an X address buffer decoder 2 and a single bit line selected by a Y address buffer decoder 3. Data is written into the selected memory cell or data stored in the memory cell is read out. Writing/reading of data is commanded by a read/write control signal (R/W) applied to a R/W control circuit 4. When data is written, input data (Din) is inputted to the selected memory cell through the R/W control circuit 4. On the other hand, when data is read out, the data stored in the selected memory cell is detected and then amplified by a sense amplifier 5, and outputted to the exterior as output data (Dout) through a data output buffer 6.
FIG. 2 is a diagram of an equivalent circuit of a dynamic type memory cell for explaining write/read operation of the memory cell. Referring to FIG. 2, the dynamic type memory cell comprises a single field effect transistor 8 and a capacitor 9. A gate electrode of the field effect transistor 8 is connected to a word line 10, and a source/drain electrode connected to the capacitor 9 is connected to a bit line 7. When data is written, the field effect transistor 8 is rendered conductive by application of a predetermined potential to the word line 10, so that electric charge applied to the bit line 7 is stored in the capacitor 9. On the other hand, when data is read out, charge stored in the capacitor 9 is extracted through the bit line 7 because the field effect transistor 8 is rendered conductive by application of a predetermined potential to the word line 10. Thus, since storage capacitance of the memory cell depends on capacitance of the capacitor 9, a trench memory cell in which a trench is formed on the semiconductor substrate and a charge storage region is formed on the inner surface of the trench so that storage capacitance can be maintained or increased, was developed for achieving high integration of the memory cell arrays.
FIG. 3 is a plan view of a dynamic RAM of a folded bit line type using the trench memory cell, and FIG. 4 is a cross sectional view taken along a line IV--IV shown in FIG. 3. The trench memory cell was proposed in, for example, Lecture Number 9.6 in International Electron Device Meeting, 1984 (IEDM '84).
Referring to FIGS. 3 and 4, a plurality of memory cells 12 are formed on the surface of a P type semiconductor substrate 11, the memory cells 12 being isolated by isolating oxide films 14. Each of the memory cells 12 comprises a charge storage region 16 for storing charge, a transfer gate region 18, and an n type impurity region 20 connected to a bit line 22. The charge storage region 16 comprises a trench 24 (a region enclosed by a solid line in FIG. 3) formed on the major surface of the semiconductor substrate 11, an n.sup.+ impurity region 30 formed on a part of the major surface of the semiconductor substrate 11 including the inner surface of the trench 24, a capacitor insulating film 32 covering the inner surface of the trench 24, and a cell plate 28 formed of polysilicon (polycrystalline silicon) or the like with which the trench 24 is filled through the capacitor insulating film 32. The transfer gate region 18 comprises a channel region 34 between the impurity region 20 and the n.sup.+ impurity region 30 and a word line 26 serving as a gate electrode over the channel region 34 and formed of polysilicon or the like. The impurity region 20, the transfer gate region 18 and the n.sup.+ impurity region 30 constitute a switching transistor. Referring to FIG. 4, description is made on write/read operation of data in FIG. 2. At the time of writing data, when a predetermined potential is applied to the word line 26, an inversion layer is formed in the channel region 34, so that the impurity region 20 and the n.sup.+ impurity region 30 are rendered conductive. Thus, charge applied to the bit line 22 is transferred to the charge storage region 16 through the channel region 34 and stored in the n.sup.+ impurity region 30. On the other hand, at the time of reading out data, when a predetermined potential is applied to the word line 26, the charge stored in the n.sup.+ impurity region 30 is extracted to the exterior through the inverted channel region 34, the impurity region 20 and the bit line 22.
Since the amount of thus stored charge depends on the size of the N.sup.+ impurity region 30 facing the trench 24, that is, the area of the inner surface of the trench 24, formation of the trench 24 can contribute to formation of larger charge storage capacitance, as compared with the plane area occupied by the charge storage region 16. More specifically, if the trench 24 is formed and a trench capacitor utilizing the trench 24 is used, a charge storage capacitor having relatively large capacitance, as compared with the area occupied by a fine memory cell can be ensured. As a result, even a highly integrated dynamic RAM becomes a reliable memory device which is immune to soft errors caused by irradiation of alpha rays or the like and the other noise, since operating margin becomes sufficiently large through the capacitor having large capacitance.
However, the use of the trench capacitor has the above described advantage but presents a new problem to a dynamic RAM requiring high integration.
FIG. 5 is an enlarged cross sectional view of trenches of adjacent two memory cells shown in FIG. 4.
Generally, in a dynamic RAM, a P type semiconductor substrate 11 is set to a negative potential (about -3V) and a potential of about 5V or about 0V corresponding to memory information "1" or "0" is applied to n.sup.+ impurity regions 30a and 30b serving as charge storage regions. Thus, a reverse-bias voltage is always applied between the n.sup.+ impurity regions 30a and 30b and the semiconductor substrate 11, irrespective of the memory information. As a result, depletion regions 36a and 36b are formed around the n.sup.+ impurity regions 30a and 30b. The higher the reverse-bias voltage is or the lower the impurity concentration of the semiconductor substrate is, the more easily the depletion regions 36a and 36b expand. Since the P type impurity concentration of the semiconductor substrate 11 becomes generally lower in the position spaced apart from the major surface, the depletion regions 36a and 36b expand as shown in FIG. 5. As a result, if trenches 24a and 24b are formed deep to increase storage capacitance, the distance between the adjacent depletion regions 36a and 36b (represented by a in FIG. 5) is further reduced. In addition, it is obvious that the distance is also reduced if trenches 28a and 28b are formed close to each other for high integration. Thus, if the adjacent trenches 28a and 28b are formed closer to each other and the trenches are formed deeper to achieve higher integration, a punch through phenomenon (a = 0) finally occurs in which the depletion regions 36a and 36b come in contact with each other. If the punch through phenomenon occurs, conduction occurs between the adjacent memory cells, so that the potentials stored in the n.sup.+ impurity regions 30a and 30b interfere with each other by the difference in memory information of the adjacent memory cells. As a result, the characteristic of holding information is deteriorated.
Therefore, it becomes difficult to form the adjacent trenches 24a and 24b at a shorter distance and form the trenches deeper, which presents a large problem for high integration of the memory cells. To prevent this, some approaches have been proposed. For example, the impurity concentration of the semiconductor substrate 11 is increased. Alternatively, an epitaxial growth substrate is used as the semiconductor substrate 11. If the impurity concentration is increased, the expansion of the depletion regions can be surely controlled. However, the widths of the depletion regions are decreased, so that the junction breakdown voltage between the n.sup.+ impurity regions and the semiconductor substrate is reduced. In addition, since the impurity concentration is further increased in the vicinity of the major surface of the semiconductor substrate 11, it becomes difficult to control the threshold voltage of the switching transistor. On the other hand, the approach of using the epitaxial growth substrate is effective. However, the substrate becomes expensive. In addition, since an epitaxial growth process is added, the manufacturing process is further complicated.
In addition, a method for manufacturing a dynamic RAM having a capacitor formed of polysilicon-polysilicon by utilizing a trench is disclosed in Japanese Patent Laying-Open Gazette No. 177771/1986 by Masahiro Hatanaka et al., entitled "Method for Manufacturing Semiconductor Device".
Furthermore, a semiconductor device in which a capacitor is further formed of polysilicon-polysilicon by utilizing a trench so that the amount of stored charges is increased disclosed in Japanese Patent Laying-Open Gazette No. 253255/1985 by Takayuki Matsukawa et al., entitled "Semiconductor Device".
However, both of the above described documents disclose a dynamic RAM having a structure for increasing the amount of stored charges by utilizing only a single trench but do not disclose an approach for solving the above described interference between adjacent trenches. Thus, the above described disclosures fail to solve the problems to be solved by the present invention or suggest solutions thereof.